1. Field of the Invention
The present invention relates to a central processing unit for performing an interruption processing at a high speed.
2. Description of the Related Art
In a central processing unit, a specific processing sequence is generally executed by an external signal. Interruption or exception processing is an example of a specific processing sequence. There are several kinds of interruption or exception processings. There are external interruptions (hardware interruptions) such as reset, maskable interrupt (IRQ), non maskable interrupt (NMI), bus error interrupt, etc. There are also internal interruptions such as a software interrupt.
U.S. Pat. No. 4,037,204 shows a method for generating a specific code in an instruction register at the time of an external interruption. In this method, it is possible to commonly perform the interruption processing by generating an interruption signal having the same code for a hardware interruption for a software interruption.
However, the respective interruption processings are different from each other and all addresses for storing interruption vectors are also different from each other. When a sequence of these interruptions is processed and the hardware and software interruptions hardware and software are performed by the common code mentioned above, the interruption processing is limited by the processing flow requiring the a longest processing time and a useless cycle (dummy cell) is disposed in the processing requiring a processing time shorter than the longest processing time, thereby reducing processing speed. Further, when there is no software interruption or a specific code different from that in the software interruption is assigned in an instruction system, this code cannot be used in the instruction system so that the instruction code is useless.